SH7047 Datasheet, PDF (456/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

Initial
Bit Bit Name Value R/W
5
MCR5
0
R/W
4, 3 —
All 0 R
Description
HCAN2 Sleep Mode
This bit enables or disables mode shift to sleep mode.
When this bit is set to 1, mode shift to sleep mode is
enabled. The HCAN2 enters sleep mode after current bus
access finished. The HCAN2 ignores the CAN bus
operation until sleep mode is finished. The values of two
error counters (REC and TEC) are not changed in sleep
mode and the subsequent mode. There are two methods
to clear sleep mode:
• Clear this bit to 0
• When MCR7 is enabled, detects the dominant bit on
the CAN bus
To clear sleep mode, HCAN2 makes synchronization with
the CAN bus by checking 11 recessive bits before joining
in the CAN bus activity. It means that the HCAN2 cannot
receive the first message when the above second method
is used. Also the CAN transceiver has the same feature.
Therefore, the software should be designed in this
manner.
Note:
This mode is as same as halt mode or stopping
the clock. It means that an interrupt is generated
by IRR0 when mode shift to sleep mode is
performed. In sleep mode, only the MPI block
(MCR, GSR, IRR and IMR) can be accessed.
However, IRR1 cannot be cleared in sleep
mode, since IRR1 is ORed with the RXPR signal
which cannot be cleared in sleep mode. It is
recommended that first set halt mode, clear the
source register for IRR setting, clear halt mode,
and then make transition to sleep mode.
0: HCAN2 sleep mode is cleared
1: Transition to HCAN2 sleep mode is enabled
Note:
The mailboxes should not be accessed in
HCAN2 sleep mode. If the mailboxes are
accessed in HCAN2 sleep mode, CPU may stop.
However, the CPU does not stop when registers
that are not relevant to mailboxes are accessed
in sleep mode or mailboxes are accessed in
other modes.
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 2.00, 09/04, page 416 of 720