SH7047 Datasheet, PDF (471/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

• TXPR0
Bit Bit Name
15 TXPR15
14 TXPR14
13 TXPR13
12 TXPR12
11 TXPR11
10 TXPR10
9
TXPR9
8
TXPR8
7
TXPR7
6
TXPR6
5
TXPR5
4
TXPR4
3
TXPR3
2
TXPR2
1
TXPR1
0

Initial Value R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R
Description
Set a transmit wait (CAN bus arbitration wait) for the
corresponding mailboxes from 1 to 15. When TXPRn
(n = 1 to 15) is set to 1, the message in mailbox n
enters transmit wait state.
0: Transmit message in corresponding mailbox is in
idle state
1: Transmit message in corresponding mailbox is
waiting for transmit
[Clearing conditions]
• Completion of message transmission
• Completion of transmission abort
Bit 0 is reserved. This bit is always read as 0. The
write value should always be 0.
TXPR flags can be cleared only when the messages
are transmitted normally.
Note: 1 can be written only when the mailbox is
configured as a transmit mailbox.
Rev. 2.00, 09/04, page 431 of 720