SH7047 Datasheet, PDF (233/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

10.3.15 Timer Period Data Register (TCDR)
TCDR is a 16-bit register used only in complementary PWM mode. Set half the PWM carrier
sync value as the TCDR register value. This register is constantly compared with the TCNTS
counter in complementary PWM mode, and when a match occurs, the TCNTS counter switches
direction (decrement to increment). The initial value is H'FFFF.
Note: Accessing the TCDR in 8-bit units is prohibited. Always access in 16-bit units.
10.3.16 Timer Period Buffer Register (TCBR)
The timer period buffer register (TCBR) is a 16-bit register used only in complementary PWM
mode. It functions as a buffer register for the TCDR register. The TCBR register values are
transferred to the TCDR register with the transfer timing set in the TMDR register. The initial
value is H'FFFF.
Note: Accessing the TCBR in 8-bit units is prohibited. Always access in 16-bit units.
10.3.17 Bus Master Interface
The timer counters (TCNT), general registers (TGR), timer subcounter (TCNTS), timer period
buffer register (TCBR), and timer dead time data register (TDDR), and timer period data register
(TCDR) are 16-bit registers. A 16-bit data bus to the bus master enables 16-bit read/writes. 8-bit
read/write is not possible. Always access in 16-bit units.
All registers other than the above registers are 8-bit registers. These are connected to the CPU by
a 16-bit data bus, so 16-bit read/writes and 8-bit read/writes are both possible.
Rev. 2.00, 09/04, page 193 of 720