SH7047 Datasheet, PDF (619/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

Section 21 RAM
The SH7047 group has an on-chip high-speed static RAM. The on-chip RAM is connected to the
CPU, data transfer controller (DTC), and advanced user debugger (AUD) by a 32-bit data bus,
enabling 8, 16, or 32-bit width access to data in the on-chip RAM. Data in the on-chip RAM can
always be accessed in one cycle, providing high-speed access that makes this RAM ideal for use
as a program area, stack area, or data area. The contents of the on-chip RAM are retained in both
sleep and software standby modes.
The on-chip RAM can be enabled or disabled by means of the RAME bit in the system control
register (SYSCR). For details on the system control register (SYSCR), refer to section 24.2.2,
System Control Register (SYSCR).
Product Type
SH7047
Type of ROM
Flash memory
Mask ROM
RAM Capacity
12 kbytes
8 kbytes
RAM Address
H'FFFFD000 to
H'FFFFFFFF
H'FFFFE000 to
H'FFFFFFFF
21.1 Usage Note
• Module Standby Mode Setting
RAM can be enabled/disabled by the module standby control register. The initial value enables
RAM operation. RAM access is disabled by setting the module standby mode. For details, see
section 24, Power-Down Modes.
Rev. 2.00, 09/04, page 579 of 720