SH7047 Datasheet, PDF (749/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

Item
Page Revisions (See Manual for Details)
15.1 Features
407,
Communication speed: Max. 1 Mbps
408
:
HCAN2 halt mode
Deleted
• Other feature
The DTC can be activated by message receive mailbox
(HCAN2 mailbox 0 only)
• Module standby mode can be set
• Read section 15.8, Usage Notes.
409 Timer: . . . Two compare match registers generate the
interrupt signal to clear the counter values and set the local
offset registers.
15.2 Input/Output Pins
410 When using HCAN2 pins, settings must be made in HCAN2
configuration mode.
410 A Renesas HA13721 compatible model is recommended.
15.3 Register Descriptions 410 • Transmit wait registers (TXPR1, TXPR0)
• Transmit wait cancel registers (TXCR1, TXCR0)
• Transmit acknowledge registers (TXACK1, TXACK0)
• Abort acknowledge registers (ABACK1, ABACK0)
• Receive complete registers (RXPR1, RXPR0)
• Remote request registers (RFPR1, RFPR0)
• Mailbox interrupt mask registers (MBIMR1, MBIMR0)
• Unread message status registers (UMSR1, UMSR0)
15.3.1 Master Control
Register (MCR)
413 to HCAN → HCAN2
418
15.3.1 Master Control
Register (MCR)
414 Bit 11:
Disable Error Counters
Enables/disables the error counters (TEC/REC) to be
functional. When this bit is enabled, the error counters
(TEC/REC) remain unchanged and holds the current value.
When this bit is disabled, the error counters (TEC/REC)
function according to the CAN specification.
415 Bit 8:
Enable Internal Loop
Enables/disables the internal TX looped back to the internal
Rx. Deleted
0: Rx is fed from the Rx Pin
Rev. 2.00, 09/04, page 709 of 720