SH7047 Datasheet, PDF (682/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

25.3.13 H-UDI Timing
Table 25.15 shows H-UDI timing.
Table 25.15 H-UDI Timing
Conditions: V_CC = 5.0 V ±0.5 V, AV_CC = 5.0 V ±0.5 V, V_SS = PLLV_SS = AV_SS = 0 V, T_a = –20°C to
+75°C (Standard product)*¹, T_a = –40°C to +85°C (Wide temperature-range
product)*¹
Item
Symbol Min
Max
Unit Figures
TCK clock cycle
t_tcyc
60*²
—
ns
Figure 25.23
TCK clock high-level width
t
TCKH
0.4
0.6
t
tcyc
TCK clock low-level width
TRST pulse width
TRST setup time
t
TCKL
t
TRSW
t_TRSS
0.4
0.6
t
tcyc
20
—
t
Figure 25.24
tcyc
30
—
ns
TMS setup time
t_TMSS
15
—
ns
Figure 25.25
TMS hold time
t_TMSH
10
—
ns
TDI setup time
t_TDIS
15
—
ns
TDI hold time
t_TDIH
10
—
ns
TDO delay time
t
—
30
ns
TDOD
Notes: 1. See page 2 for correspondence of the standard product, wide temperature-range
product, and product model name.
2. Must not be lower than 2 t_cyc.
t_TCKH
t_TCKL
TCK
V_IH
V_IH
V_IL
t_tcyc
V_IH
V_IL
Figure 25.23 H-UDI Clock Timing
Rev. 2.00, 09/04, page 642 of 720