SH7047 Datasheet, PDF (685/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

CK
(Branch trace)
AUDCK (input)
(RAM monitor)
AUDRST
AUDMD
t_cyc
t_RMCYC
t_AUDRSTW
t_AUDMDS
Figure 25.26 AUD Reset Timing
AUDCK
(output)
AUDATA3 to
AUDATA0
(output)
AUDSYNC
(output)
t_BTCKW
t_BTDD
t_BTSD
t_BTCYC
t_BTDH
t_BTSH
Figure 25.27 Branch Trace Timing
AUDCK
(input)
AUDATA3 to
AUDATA0
(output)
AUDATA3 to
AUDATA0
(input)
AUDSYNC
(input)
t_RMCYC
t_RMCKW
t_RMDD
t_RMDHD
t_RMDS
t_RMDH
t_RMSS
t_RMSH
Figure 25.28 RAM Monitor Timing
Rev. 2.00, 09/04, page 645 of 720