SH7047 Datasheet, PDF (527/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

16.3.1 Timer Mode Register (MMT_TMDR)
The timer mode register (MMT_TMDR) sets the operating mode and selects the PWM output
level. In this section, the name of this register is abbreviated to TMDR hereafter.
Initial
Bit Bit Name Value
7—
0
6 CKS2
0
5 CKS1
0
4 CKS0
0
3 OLSN
0
2 OLSP
0
1 MD1
0
0 MD0
0
R/W Description
R
Reserved
These bits are always read as 0 and should only be
written with 0.
R/W Clock Select 2 to 0
R/W Selects the clock input to MMT.
R/W 000: Pφ
001: Pφ/4
010: Pφ/16
011: Pφ/64
100: Pφ/256
101: Pφ/1024
11X: Setting prohibited.
Note: X “don't care”.
R/W Output Level Select N
Selects the negative phase output level in the operating
modes.
0: Active level is low
1: Active level is high
R/W Output Level Select P
Selects the positive phase output level in the operating
modes.
0: Active level is low
1: Active level is high
R/W Mode 0 to 3
R/W These bits set the timer operating mode.
00: Operation halted
01: Operating mode 1 (Transfer at TCNT = TPDR)
10: Operating mode 2 (Transfer at TCNT = TDDR × 2)
11: Operating mode 3 (Transfer at TCNT = TPDR or
TCNT = TDDR × 2)
Rev. 2.00, 09/04, page 487 of 720