SH7047 Datasheet, PDF (365/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

11.4.5 Timing of Setting the Watchdog Timer Overflow Flag (WOVF)
When TCNT overflows in watchdog timer mode, the WOVF bit of RSTCSR is set to 1 and a
WDTOVF signal is output. When the RSTE bit in RSTCSR is set to 1, TCNT overflow enables an
internal reset signal to be generated for the entire chip. Figure 11.5 shows this timing.
φ
TCNT
Overflow signal
(internal signal)
H'FF H'00
WOVF
Figure 11.5 Timing of Setting WOVF
11.5 Interrupts
During interval timer mode operation, an overflow generates an interval timer interrupt (ITI). The
interval timer interrupt is requested whenever the OVF flag is set to 1 in TCSR. OVF must be
cleared to 0 in the interrupt handling routine.
Table 11.2 WDT Interrupt Source (in Interval Timer Mode)
Name
ITI
Interrupt Source
TCNT overflow
Interrupt Flag
OVF
DTC Activation
Impossible
11.6 Usage Notes
11.6.1 Notes on Register Access
The watchdog timer’s TCNT, TCSR, and RSTCSR registers differ from other registers in being
more difficult to write to. The procedures for writing to and reading these registers are given
below.
Writing to TCNT and TCSR: These registers must be written by a word transfer instruction.
They cannot be written by byte transfer instructions.
Rev. 2.00, 09/04, page 325 of 720