SH7047 Datasheet, PDF (477/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

• ABACK0
Bit Bit Name
15 ABACK15
14 ABACK14
13 ABACK13
12 ABACK12
11 ABACK11
10 ABACK10
9
ABACK9
8
ABACK8
7
ABACK7
6
ABACK6
5
ABACK5
4
ABACK4
3
ABACK3
2
ABACK2
1
ABACK1
0

Initial Value R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R/W
0
R
Description
Status flags that indicate error-free cancellation of
the transmit message in the corresponding
mailboxes from 1 to 15. When the message in
mailbox n (n = 1 to 15) has been canceled error-free,
ABACKn is set to 1.
[Setting condition]
• Completion of transmit message abort for
corresponding mailbox
[Clearing condition]
• Writing 1
Bit 0 is reserved. This bit is always read as 0. The
write value should always be 0.
Note: Writing operation by the CPU is valid only for
clearing condition (writing 1) of set status.
Rev. 2.00, 09/04, page 437 of 720