SH7047 Datasheet, PDF (455/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

Initial
Bit Bit Name Value R/W Description
9
TST1
0
R/W Disable Tx Output
Controls the Tx Output pin to output transmit data or
recessive bits. If this bit is enabled, the internal transmit
output value appears on the Tx pin. If this bit is disabled,
the Tx Output pin always remains recessive.
0: External Tx pin is supplied for the CAN Interface block
1: [TST0 = 0] Tx always recessive on the Tx pin
[TST0 = 1] Tx is internally looped backed to the Internal
Rx
8
TST0
0
R/W Enable Internal Loop
Enables/disables the internal TX looped back to the
internal Rx.
0: Rx is fed from the Rx Pin
1: Rx is fed back from the internal Tx signal
7
MCR7
0
R/W HCAN2 Sleep Mode Release
When this bit is set to 1, the HCAN2 automatically exits
HCAN2 sleep mode on detection of CAN bus operation.
6
—
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
Rev. 2.00, 09/04, page 415 of 720