SH7047 Datasheet, PDF (511/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

• Remote frame reception
Two kinds of messages—data frames and remote frames—can be stored in mailboxes. A
remote frame differs from a data frame in that the value of the remote transmission request bit
(RTR) in the message control and the data field are 0 bytes long. The data length to be returned
in a data frame must be stored in the data length code (DLC) in the control field.
When a remote frame (RTR = recessive) is received, the corresponding bit is set in the remote
request wait register (RFPR). If the corresponding bit (MBIMR0 to MBIMR31) in the mailbox
interrupt mask register (MBIMR) and the remote frame request interrupt mask (IRR2) in the
interrupt mask register (IMR) are set to the interrupt enable value at this time, an interrupt
request (RM1) can be sent to the CPU.
Unread Message Overwrite: If the receive message identifier matches the mailbox identifier, the
receive message is stored in the mailbox regardless of whether the mailbox contains an unread
message or not. If a message overwrite occurs, the corresponding bit (UMSR0 to UMSR31) is set
in the unread message register (UMSR). In overwriting an unread message, when a new message
is received before the corresponding bit in the receive complete register (RXPR) has been cleared,
the unread message register (UMSR) is set. If the unread interrupt flag (IRR9) in the interrupt
mask register (IMR) is set to the interrupt enable value at this time, an interrupt can be sent to the
CPU. Figure 15.11 shows a flowchart for unread message overwriting.
Unread message overwrite
UMSR = 1
IRR9 = 1
: Settings by user
: Processing by hardware
IMR9 = 1?
Yes
No
Interrupt to CPU (OVR1)
Clear IRR9
Message control/message data read
End
Figure 15.11 Unread Message Overwrite Flowchart
Rev. 2.00, 09/04, page 471 of 720