SH7047 Datasheet, PDF (487/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

Register
Data Bus
Access
Name Address 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Size
Field
MBx[0] to H'100 + 0
[1]
N*32
STDID[10:0]
RTR IDE EXTID Word
[17:16] (16 bits)
Control
MBx[2] to H'102 +
[3]
N*32
EXTID[15:0]
MBx[4] to H'104 + CCM 0 NMC ATX DART
[5]
N*32
MBC[2:0]
0 TCT 0 0
DLC[3:0]
Byte (8 bits)
or word (16
bits)
MBx[6] H'106 +
N*32
Timestamp[15:0]
Word
(16 bits)
Timestamp
MBx[7] to H'108 +
[8]
N*32
MBx[9] to H'10A +
[10]
N*32
MSG_DATA_0 (first Rx/Tx byte)
MSG_DATA_2
MSG_DATA_1
MSG_DATA_3
Byte (8 bits) ^Data
or word (16
bits)
MBx[11] H'10C +
to [12] N*32
MSG_DATA_4
MSG_DATA_5
MBx[13] H'10E +
to [14] N*32
MSG_DATA_6
MSG_DATA_7
MBx[15] H'110 +
to [16] N*32
Local acceptance filter mask 0 (LAFM0)
Word
(16 bits)
LAFM
MBx[17] H'112 +
to [18] N*32
Local acceptance filter mask 1 (LAFM1)
Note: Shaded bits are reserved. The write value should always be 0. The read value is not
guaranteed.
Figures 15.3 (standard format) and 15.4 (extended format) show the correspondence between the
identifiers (ID) and register bit names.
SOF ID-10 ID-9
ID-0 RTR IDE R0
Identifier
STDID[10:0]
Figure 15.3 Standard Format
SOF ID-28 ID-27
ID-18 SRR IDE ID-17 ID-16
ID-0 RTR R1
Base identifier
STDID[10:0]
Extended identifier
EXTIDC[17:0]
Figure 15.4 Extended Format
The following table lists mailbox settings.
An x for register name MBx indicates mailbox number.
Rev. 2.00, 09/04, page 447 of 720