SH7047 Datasheet, PDF (232/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

Initial
Bit Bit Name value R/W Description
2
WF
0
R/W Output Phase Switch 2 to 0
1
VF
0
UF
0
R/W These bits set the positive phase/negative phase output
0
R/W ^{phase on or off state. The setting of these bits is valid only}
when the FB bit in this register is set to 1. In this case, the
setting of bits 2 to 0 is a substitute for external input. See
table 10.28.
Table 10.28 Output level Select Function
Bit 2
WF
0
1
Bit 1
VF
0
1
0
1
Bit 0
UF
0
1
0
1
0
1
0
1
TIOC3B
U Phase
OFF
ON
OFF
OFF
OFF
ON
OFF
OFF
TIOC4A
V Phase
OFF
OFF
ON
ON
OFF
OFF
OFF
OFF
Function
TIOC4B TIOC3D
W Phase U Phase
OFF
OFF
OFF
OFF
OFF
ON
OFF
OFF
ON
OFF
OFF
OFF
ON
ON
OFF
OFF
TIOC4C
V Phase
OFF
OFF
OFF
OFF
ON
ON
OFF
OFF
TIOC4D
W Phase
OFF
ON
OFF
ON
OFF
OFF
OFF
OFF
10.3.13 Timer Subcounter (TCNTS)
TCNTS is a 16-bit read-only counter that is used only in complementary PWM mode. The initial
value is H'0000.
Note: Accessing the TCNTS in 8-bit units is prohibited. Always access in 16-bit units.
10.3.14 Timer Dead Time Data Register (TDDR)
TDDR is a 16-bit register, used only in complementary PWM mode, that specifies the TCNT_3
and TCNT_4 counter offset values. In complementary PWM mode, when the TCNT_3 and
TCNT_4 counters are cleared and then restarted, the TDDR register value is loaded into the
TCNT_3 counter and the count operation starts. The initial value is H'FFFF.
Note: Accessing the TDDR in 8-bit units is prohibited. Always access in 16-bit units.
Rev. 2.00, 09/04, page 192 of 720