SH7047 Datasheet, PDF (186/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

9.8 Bus Arbitration
This LSI has a bus arbitration function that, when a bus release request is received from an
external device, releases the bus to that device. It also has three internal bus masters, the CPU,
DTC, and AUD (only for flash version). The priority for arbitrate the bus mastership between
these bus masters is:
Bus request from external device > AUD > DTC > CPU
A bus request by an external device should be input to the BREQ pin. When the BREQ pin is
asserted, this LSI releases the bus immediately after the bus cycle being executed is completed.
The signal indicating that the bus has been released is output from the BACK pin.
However, the bus is not released between the read and write cycles during TAS instruction
execution. Bus arbitration is not executed between multiple bus cycles that occur due to the data
bus width smaller than access size, for instance, bus cycles in which 8-bit memory is accessed by a
longword.
The bus may be returned when this LSI is releasing the bus. That is, when interrupt request occurs
to be processed. This LSI incorporates the IRQOUT pin for the bus request signal. When the bus
must be returned to this LSI, the IRQOUT signal can be asserted. The device that is asserting an
external bus-release request negates the BREQ signal to release the bus when the IRQOUT signal
is asserted. As a result, the bus is returned to and processed by this LSI.
The asserting condition of the IRQOUT pin is that an interrupt source occurs and the interrupt
request level is higher than that of interrupt mask bits I3 to I0 in status register SR.
Figure 9.8 shows the bus mastership release procedure.
Rev. 2.00, 09/04, page 146 of 720