SH7047 Datasheet, PDF (156/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

8.2.8 DTC Control/Status Register (DTCSR)
The DTCSR is a 16-bit readable/writable register that disables/enables DTC activation by software
and sets the DTC vector addresses for software activation. It also indicates the DTC transfer
status.
Bit
Bit Name
15 to 11 
Initial
Value
All 0
10
NMIF
0
9
AE
0
8
SWDTE 0
R/W Description
R
Reserved
These bits have no effect on DTC operation and
should always be written with 0.
R/(W)*¹ NMI Flag Bit
This bit indicates that an NMI interrupt has occurred.
0: No NMI interrupts
[Clearing condition]
• Write 0 after reading the NMIF bit
1: NMI interrupt has been generated
R/(W)*¹
When the NMIF bit is set, DTC transfers are not
allowed even if the DTER bit is set to 1. If, however, a
transfer has already started with the NMIM bit of the
DTMR set to 1, execution will continue until that
transfer ends.
Address Error Flag
This bit indicates that an address error by the DTC
has occurred.
0: No address error by the DTC
[Clearing condition]
• Write 0 after reading the AE bit
1: An address error by the DTC occurred
When the AE bit is set, DTC transfers are not allowed
even if the DTER bit is set to 1.
R/W*² DTC Software Activation Enable
Setting this bit to 1 activates DTC.
0: DTC activation by software disabled
1: DTC activation by software enabled
Rev. 2.00, 09/04, page 116 of 720