SH7047 Datasheet, PDF (180/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

9.5.3 Wait Control Register 1 (WCR1)
WCR1 is a 16-bit readable/writable register that specifies the number of wait cycles for CS0
space.
Bit Bit Name
15 to 4 
Initial
Value
All 1
3
W03
1
2
W02
1
1
W01
1
0
W00
1
R/W Description
R/W Reserved
These bits are always read as 1 and should always be
written with 1.
R/W CS0 Space Wait Specification
R/W These bits specify the number of waits for CS0 space
R/W
access.
R/W
0000: No wait (external wait input disabled)
0001: One wait (external wait input enabled)
...
1111: 15 wait (external wait input enabled)
9.5.4 RAM Emulation Register (RAMER)
The RAM emulation register (RAMER) is a 16-bit readable/writable register that selects the RAM
area to be used when emulating realtime programming of flash memory. For details, refer to
section 19.5.5, RAM Emulation Register (RAMER).
Rev. 2.00, 09/04, page 140 of 720