SH7047 Datasheet, PDF (302/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

10.7.7 Contention between Buffer Register Write and Compare Match
If a compare match occurs in the T2 state of a TGR write cycle, the data that is transferred to TGR
by the buffer operation differs depending on channel 0 and channels 3 and 4: data on channel 0 is
that after write, and on channels 3 and 4, before write.
Figures 10.74 and 10.75 show the timing in this case.
Pφ
Address
Write signal
Compare
match signal
Compare
match buffer
signal
Buffer register
TGR write cycle
T1 T2
Buffer register
address
Buffer register write data
N
M
TGR
M
Figure 10.74 Contention between Buffer Register Write and Compare Match (Channel 0)
Rev. 2.00, 09/04, page 262 of 720