SH7047 Datasheet, PDF (223/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

Initial
Bit Bit Name value R/W Description
3
TGFD
0
R/(W) Input Capture/Output Compare Flag D
Status flag that indicates the occurrence of TGRD input
capture or compare match in channels 0, 3, and 4. Only 0
can be written, for flag clearing. In channels 1 and 2, bit 3 is
reserved. It is always read as 0, and should only be written
with 0.
[Setting conditions]
• When TCNT = TGRD and TGRD is functioning as output
compare register
• When TCNT value is transferred to TGRD by input
capture signal and TGRD is functioning as input capture
register
[Clearing conditions]
• When DTC is activated by TGID interrupt and the DISEL
bit of DTMR in DTC is 0
• When 0 is written to TGFD after reading TGFD = 1
2
TGFC
0
R/(W) Input Capture/Output Compare Flag C
Status flag that indicates the occurrence of TGRC input
capture or compare match in channels 0, 3, and 4. Only 0
can be written, for flag clearing. In channels 1 and 2, bit 2 is
reserved. It is always read as 0, and should only be written
with 0.
[Setting conditions]
• When TCNT = TGRC and TGRC is functioning as output
compare register
• When TCNT value is transferred to TGRC by input
capture signal and TGRC is functioning as input capture
register
[Clearing conditions]
• When DTC is activated by TGIC interrupt and the DISEL
bit of DTMR in DTC is 0
• When 0 is written to TGFC after reading TGFC = 1
Rev. 2.00, 09/04, page 183 of 720