SH7047 Datasheet, PDF (453/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

15.3.1 Master Control Register (MCR)
MCR is a 16-bit register that controls the HCAN2 operation.
Initial
Bit Bit Name Value R/W Description
15 TST7
0
R/W Test Mode
Enables/disables the test modes settable by TST[6:0].
When this bit is set, the following TST[6:0] become
effective.
0: HCAN2 is in normal mode
1: HCAN2 is in test mode
14 TST6
0
R/W Write CAN Error Counters
Enables the TEC (Transmit Error Counter) and REC
(Receive Error Counter) to be writable. The same value
can only be written into the TEC/REC at the same time.
The maximum value that can be written into the TEC/REC
is D'255 (H'FF). This means that the HCAN2 cannot be
forced into the bus off state. Before writing into the
TEC/REC, HCAN2 needs to be put into Halt Mode, and
when writing into the TEC/REC, the TST7 (MCR15) needs
to be ‘1’. Only the same value can be set between
TEC/REC, and the value written into TEC is used to write
REC.
0: TEC/REC is not writable but read-only
1: TEC/REC is writable with the same value at the same
time
13 TST5
0
R/W Force to Error Passive
Forces HCAN2 to become error passive. When this bit is
set, HCAN2 behaves as an error passive node, regardless
of the error counters.
0: State of HCAN2 depends on the error counters
1: HCAN2 behaves as an error passive node regardless of
the error counters
Rev. 2.00, 09/04, page 413 of 720