SH7047 Datasheet, PDF (647/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

24.2.1 Standby Control Register (SBYCR)
SBYCR is an 8-bit readable/writable register that performs software standby mode control.
Initial
Bit Bit Name Value
7
SSBY
0
6
HIZ
0
5

0
4 to 1 
All 1
0
IRQEL
1
R/W Description
R/W Software Standby
This bit specifies the transition mode after executing the
SLEEP instruction.
0: Shifts to sleep mode after the SLEEP instruction has
been executed
1: Shifts to software standby mode after the SLEEP
instruction has been executed
This bit cannot be set to 1 when the watchdog timer
(WDT) is operating (when the TME bit in TCSR of the
WDT is set to 1). When transferring to software standby
mode, clear the TME bit to 0, stop the WDT, then set the
SSBY bit to 1.
R/W Port High-Impedance
In software standby mode, this bit selects whether the pin
state of the I/O port is retained or changed to high-
impedance.
0: In software standby mode, the pin state is retained.
1: In software standby mode, the pin state is changed to
high-impedance.
The HIZ bit cannot be set to 1 when the TEM bit in TCSR
of the WDT is set to 1.
When changing the pin state of the I/O port to high-
impedance, clear the TEM bit to 0, then set the HIZ bit to
1.
R
Reserved
This bit is always read as 0, and should always be written
with 0.
R
Reserved
These bits are always read as 1, and should always be
written with 1.
R/W IRQ3 to IRQ0 Enable
IRQ interrupts are enabled to clear software standby
mode.
0: Software standby mode is cleared.
1: Software standby mode is not cleared.
Rev. 2.00, 09/04, page 607 of 720