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SH7047 Datasheet, PDF (571/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series
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The initial value of PDIORL is H'0000.
17.1.6 Port D Control Registers L1 and L2 (PDCRL1 and PDCRL2)
The port D control registers L1 and L2 (PDCRL1 and PDCRL2) are 16-bit readable/writable
registers that are used to select the multiplexed pin function of the pins on port D.
Port D Control Registers L1 and L2 (PDCRL1 and PDCRL2)
Register Bit
Initial
Bit Name Value R/W
PDCRL2 15 to 9 
All 0 R
PDCRL1 15 to 9 
All 0 R
PDCRL2 8
PDCRL1 8
PD8MD1 0
R/W
PD8MD0 0
R/W
PDCRL2 7
PDCRL1 7
PD7MD1 0
PD7MD0 0*2
R/W
R/W
PDCRL2 6
PDCRL1 6
PD6MD1 0
PD6MD0 0*2
R/W
R/W
PDCRL2 5
PDCRL1 5
PD5MD1 0
PD5MD0 0*2
R/W
R/W
PDCRL2 4
PDCRL1 4
PD4MD1 0
PD4MD0 0*2
R/W
R/W
PDCRL2 3
PDCRL1 3
PD3MD1 0
PD3MD0 0*2
R/W
R/W
Description
Reserved
These bits are always read as 0 and should only be
written with 0.
PD8 Mode
Select the function of the PD8/UBCTRG pin.
00: PD8 I/O (port)
10: Setting prohibited
01: Setting prohibited 11: UBCTRG output (UBC)*1
PD7 Mode
Select the function of the PD7/D7/AUDSYNC pin.
00: PD7 I/O (port)
01: D7 I/O (BSC)
10: Setting prohibited
11: AUDSYNC I/O (AUD)*1
PD6 Mode
Select the function of the PD6/D6/AUDCK pin.
00: PD6 I/O (port)
01: D6 I/O (BSC)
10: Setting prohibited
11: AUDCK I/O (AUD)*1
PD5 Mode
Select the function of the PD5/D5/AUDMD pin.
00: PD5 I/O (port)
01: D5 I/O (BSC)
10: Setting prohibited
11: AUDMD input (AUD)*1
PD4 Mode
Select the function of the PD4/D4/AUDRST pin.
00: PD4 I/O (port)
01: D4 I/O (BSC)
10: Setting prohibited
11: AUDRST input (AUD)*1
PD3 Mode
Select the function of the PD3/D3/AUDATA3 pin.
00: PD3 I/O (port)
01: D3 I/O (BSC)
10: Setting prohibited
11: AUDATA3 I/O (AUD)*1
Rev. 2.00, 09/04, page 531 of 720
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