SH7047 Datasheet, PDF (509/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

15.4.4 Message Reception
Follow the procedure below to perform message reception after initial setting. Figure 15.10 shows
a flowchart in reception.
Initialization
Clear IRR0
HCAN2 port setting
BCR setting
MBC setting
Mailbox (RAM) initialization
Interrupt settings
Receive data setting
Arbitration field setting
Local acceptance filter settings
: Settings by user
: Processing by hardware
Message reception?
(Match of identifier
in mailbox?)
Yes
Same RXPR = 1?
No
Data frame?
Yes
RXPR
IRR1 = 1
IMR1 = 1?
No
Interrupt to CPU (RM1)
Message control read
Message data read
Clear IRR1
No
Yes
Unread message
(Remote frame)
No
RXPR, RFPR = 1
IRR2 = 1, IRR1 = 1
Yes
Yes
IMR2 = 1?
No
Interrupt to CPU (RM1)
Message control read
Message data read
Clear IRR2 and IRR1
Transmission of data frame corresponding
to remote frame
End of reception
Figure 15.10 Flowchart in Reception
Rev. 2.00, 09/04, page 469 of 720