SH7047 Datasheet, PDF (146/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

7.5 Usage Notes
7.5.1 Simultaneous Fetching of Two Instructions
Two instructions may be simultaneously fetched in instruction fetch operation. Once a break
condition is set on the latter of these two instructions, a user break interrupt will occur before the
latter instruction, even though the contents of the UBC registers are modified to change the break
conditions immediately after the fetching of the former instruction.
7.5.2 Instruction Fetches at Branches
When a conditional branch instruction or TRAPA instruction causes a branch, the order of
instruction fetching and execution is as follows:
1. When branching with a conditional branch instruction: BT and BF instructions
When branching with a TRAPA instruction:
TRAPA instruction
A. Instruction fetch order
Branch instruction fetch → next instruction overrun fetch → overrun fetch of instruction
after the next → branch destination instruction fetch
B. Instruction execution order
Branch instruction execution → branch destination instruction execution
2. When branching with a delayed conditional branch instruction: BT/S and BF/S instructions
A. Instruction fetch order
Branch instruction fetch → next instruction fetch (delay slot) → overrun fetch of
instruction after the next → branch destination instruction fetch
B. Instruction execution order
Branch instruction execution → delay slot instruction execution → branch destination
instruction execution
Thus, when a conditional branch instruction or TRAPA instruction causes a branch, the branch
destination instruction will be fetched after an overrun fetch of the next instruction or the
instruction after the next. However, as the instruction that is the object of the break does not break
until fetching and execution of the instruction have been confirmed, the overrun fetches described
above do not become objects of a break.
If data accesses are also included in break conditions besides instruction fetch, a break will occur
because the instruction overrun fetch is also regarded as satisfying the data break condition.
Rev. 2.00, 09/04, page 106 of 720