SH7047 Datasheet, PDF (91/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

Section 4 Clock Pulse Generator
This LSI has an on-chip clock pulse generator (CPG) that generates the system clock (φ) and
peripheral clock (Pφ) to generate the internal clock (φ/2 to φ/8192, Pφ/2 to Pφ/1024). The CPG
consists of an oscillator, PLL circuit, and pre-scaler. A block diagram of the clock pulse generator
is shown in figure 4.1. The frequency from the oscillator can be modified by the PLL circuit.
PLLCAP
CK
EXTAL
XTAL
Oscillator
PLL circuit
Clock divider
(× 1/2)
MD2
Clock mode
MD3
control circuit
Pre-scaler
Pre-scaler
φ
φ/2 to
φ/8192
Pφ/2 to
Pφ/1024
Pφ φ/2
(HCAN2)
Within the LSI
Figure 4.1 Block Diagram of the Clock Pulse Generator
Rev. 2.00, 09/04, page 51 of 720