SH7047 Datasheet, PDF (488/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

Register
Name Bit
MBx[0], 15
MBx[1]
14 to 4
Bit Name R/W
—
R/W
STDID[10:0] R/W
3
RTR
R/W
2
IDE
R/W
1, 0
EXTID[17:16] R/W
MBx[2],
MBx[3]
MBx[4],
MBx[5]
15 to 0 EXTID[15:0] R/W
15
CCM
R/W
14

R/W
Description
The initial values of these bits are undefined; they
must be initialized (by writing 0).
Set the identifier (standard) of data frames and
remote frames.
Remote Transmission Request
Used to distinguish between data frames and remote
frames.
0: Data frame
1: Remote frame
In a case where the MBC2 to MBC0 bits in MBx[4] =
001 and ATX bit in MBx[4] = 1 (in a case where
automatic transmission function of data frame is
used), this bit will not be overwritten to 1 after
receiving remote frame.
Identifier Extension
Used to distinguish between the standard format and
extended format.
0: Standard format
1: Extended format
Set the identifier (extended) of data frames and
remote frames.
CAN-ID Compare Match
When this bit is set, the corresponding mailbox
receiving a message can trigger two actions. If the
TCR9 bit is set to 1, the reception of the message
will automatically clear the TCR14 bit (causing ICR0
to freeze). If the TCR10 bit is set to 1, the reception
of the message will automatically clear the timer
counter register (TCNTR) and set it to the local offset
register (LOSR) value.
Note:
This function is not supported in this LSI.
Therefore, the write value should always be
0. The read value is not guaranteed.
The initial values of these bits are undefined; they
must be initialized (by writing 0).
Rev. 2.00, 09/04, page 448 of 720