SH7047 Datasheet, PDF (516/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

15.4.7 HCAN2 Halt Mode
The HCAN2 halt mode is provided to enable mailbox settings to be changed without performing
an HCAN2 hardware or software reset. In HCAN2 halt mode, the contents of all registers are
retained. Figure 15.14 shows a flowchart of HCAN2 halt mode.
MCR1 = 1
No
Bus idle?
No
Yes
GSR4 = 1?
No
Yes
Mailbox setting
MCR1 = 0
?
11 recessive bits received
No
Yes
CAN bus communication possible
: Settings by user
: Processing by hardware
Figure 15.14 HCAN2 Halt Mode Flowchart
HCAN2 halt mode is entered by setting the halt request bit (MCR1) to 1 in the master control
register (MCR). If the CAN bus is operating, the transition to HCAN2 halt mode is delayed until
the bus becomes idle.
HCAN2 halt mode is cleared by clearing MCR1 to 0.
Rev. 2.00, 09/04, page 476 of 720