SH7047 Datasheet, PDF (68/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

Instruction Formats
md format
15
0
xxxx xxxx mmmm dddd
Source
Operand
mmmmdddd:
Indirect register
with displacement
Destination
Operand
R0 (Direct
register)
Example
MOV.B
@(disp,Rn),R0
nd4 format
15
xxxx xxxx
0
nnnn dddd
R0 (Direct register) nnnndddd:
Indirect register
with displacement
MOV.B
R0,@(disp,Rn)
nmd format
15
0
xxxx nnnn mmmm dddd
d format
15
xxxx xxxx
0
dddd dddd
d12 format
15
xxxx dddd
dddd
0
dddd
mmmm: Direct
register
nnnndddd: Indirect MOV.L
register with
Rm,@(disp,Rn)
displacement
mmmmdddd:
Indirect register
with displacement
nnnn: Direct
register
MOV.L
@(disp,Rm),Rn
dddddddd: Indirect R0 (Direct register) MOV.L
GBR with
@(disp,GBR),R0
displacement
R0 (Direct register) dddddddd: Indirect MOV.L
GBR with
R0,@(disp,GBR)
displacement
dddddddd: PC
relative with
displacement
R0 (Direct register) MOVA
@(disp,PC),R0

dddddddd: PC
BF
label
relative

dddddddddddd: BRA label
PC relative
(label = disp
+ PC)
nd8 format
15
xxxx nnnn
dddd
0
dddd
dddddddd: PC
relative with
displacement
nnnn: Direct
register
MOV.L
@(disp,PC),Rn
i format
15
0
xxxx xxxx i i i i i i i i
ni format
15
0
xxxx nnnn i i i i i i i i
iiiiiiii: Immediate
iiiiiiii: Immediate
iiiiiiii: Immediate
iiiiiiii: Immediate
Indirect indexed
GBR
AND.B
#imm,@(R0,GBR)
R0 (Direct register) AND #imm,R0

TRAPA #imm
nnnn: Direct
register
ADD #imm,Rn
Note: * In multiply-and-accumulate instructions, nnnn is the source register.
Rev. 2.00, 09/04, page 28 of 720