SH7047 Datasheet, PDF (544/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

16.6.2 Interrupt Signal Timing
Timing of TGF Flag Setting by Compare Match: Figure 16.12 shows the timing of setting of
the TGF flag in the timer status register (TSR) on a compare match between TCNT and TPDR,
and the timing of the TGI interrupt request signal. The timing is the same for a compare match
between TCNT and 2Td.
Pφ
TCNT
TPDR
Compare match
signal
TGF flag
N–3 N–2 N–1 N N+1 N+2 N+3 N+4
N
TGI interrupt
Figure 16.12 TGI Interrupt Timing
Status Flag Clearing Timing: A status flag is cleared when the CPU reads 1 from the flag, then 0
is written to it. When the DTC controller is activated, the flag is cleared automatically. Figure
16.13 shows the timing of status flag clearing by the CPU, and figure 16.14 shows the timing of
status flag clearing by the DTC.
Pφ
Address
TSR write cycle
T1 T2
TSR address
Write signal
Status flag
Interrupt
request
signal
Figure 16.13 Timing of Status Flag Clearing by CPU
Rev. 2.00, 09/04, page 504 of 720