SH7047 Datasheet, PDF (75/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

Arithmetic Operation Instructions:
Instruction
ADD
Rm,Rn
ADD
#imm,Rn
ADDC Rm,Rn
ADDV Rm,Rn
CMP/EQ #imm,R0
CMP/EQ Rm,Rn
CMP/HS Rm,Rn
CMP/GE Rm,Rn
CMP/HI Rm,Rn
CMP/GT Rm,Rn
CMP/PL Rn
CMP/PZ Rn
CMP/STR Rm,Rn
DIV1 Rm,Rn
DIV0S Rm,Rn
DIV0U
DMULS.L Rm,Rn
DMULU.L Rm,Rn
Instruction Code
0011nnnnmmmm1100
0111nnnniiiiiiii
0011nnnnmmmm1110
0011nnnnmmmm1111
10001000iiiiiiii
0011nnnnmmmm0000
0011nnnnmmmm0010
0011nnnnmmmm0011
0011nnnnmmmm0110
0011nnnnmmmm0111
0100nnnn00010101
0100nnnn00010001
0010nnnnmmmm1100
0011nnnnmmmm0100
0010nnnnmmmm0111
0000000000011001
0011nnnnmmmm1101
0011nnnnmmmm0101
Operation
Execution
States T Bit
Rn + Rm → Rn
1

Rn + imm → Rn
1

Rn + Rm + T → Rn, 1
Carry → T
Carry
Rn + Rm → Rn,
1
Overflow → T
Overflow
If R0 = imm, 1 → T
1
Comparison
result
If Rn = Rm, 1 → T
1
Comparison
result
If Rn ≥ Rm with
1
unsigned data, 1 → T
Comparison
result
If Rn ≥ Rm with signed 1
data, 1 → T
Comparison
result
If Rn > Rm with
1
unsigned data, 1 → T
Comparison
result
If Rn > Rm with signed 1
data, 1 → T
Comparison
result
If Rn > 0, 1 → T
1
Comparison
result
If Rn ≥ 0, 1 → T
1
Comparison
result
If Rn and Rm have
1
an equivalent byte,
1→T
Comparison
result
Single-step division 1
(Rn ÷ Rm)
Calculation
result
MSB of Rn → Q, MSB 1
of Rm → M, M ^ Q → T
Calculation
result
0 → M/Q/T
1
0
Signed operation of Rn 2 to 4* 
× Rm → MACH, MACL
32 × 32 → 64 bits
Unsigned operation of 2 to 4* 
Rn × Rm → MACH,
MACL 32 × 32 → 64
bits
Rev. 2.00, 09/04, page 35 of 720