SH7047 Datasheet, PDF (469/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

15.3.7 Error Counter Register (TEC/REC)
The error counter register is a 16-bit read-only register composed of the transmit error counter
(TEC) and receive error counter (REC).
TEC is an 8-bit register that functions as a counter indicating the number of transmit message
errors on the CAN bus. The count value is stipulated in the CAN protocol.
REC is an 8-bit register that functions as a counter indicating the number of receive message
errors on the CAN bus. The count value is stipulated in the CAN protocol.
Bit Bit Name Initial Value R/W Description
15 TEC7
0
R
Transmit Error Counter
14 TEC6
0
13 TEC5
0
R
This register can be cleared by a reset request
R
(MCR0) or the bus off state.
12 TEC4
0
R
11 TEC3
0
R
10 TEC2
0
R
9
TEC1
0
R
8
TEC0
0
R
7
REC7
0
R
Receive Error Counter
6
REC6
0
5
REC5
0
R
This register can be cleared by a reset request
R
(MCR0) or the bus off state.
4
REC4
0
R
3
REC3
0
R
2
REC2
0
R
1
REC1
0
R
0
REC0
0
R
Rev. 2.00, 09/04, page 429 of 720