SH7047 Datasheet, PDF (457/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

Initial
Bit Bit Name Value R/W Description
2
MCR2
0
R/W Message Transmission Method
0: Transmission order determined by message identifier
priority
1: Transmission order determined by mailbox number
priority (TXPR30 > TXPR1)
1
MCR1
0
R/W HCAN2 Halt Mode
When this bit is set to 1, the HCAN2 completes current
operation and then disconnects the CAN bus. The
HCAN2 remains in halt mode until this bit is cleared.
During halt mode, the CAN interface does not join in the
CAN bus activity or neither store nor transmit messages.
The contents of all registers and mailboxes remain.
If the HCAN2 is in transmission or reception, the HCAN2
completes the operation and enters halt mode. If the CAN
bus is in the idle state or intermission state, HCAN2
enters halt mode immediately. IRR0 and GST4 notify that
the HCAN has entered halt mode. If a halt request is
made during bus off, HCAN2 remains bus off even after
128 × 11 recessive bits. To exit this state, halt mode
should be cleared by the software.
Since the HCAN2 does not join in the bus activity in halt
mode, the HCAN2 configuration can be changed. To join
in the CAN bus activity, this bit need to be cleared to 0.
After this bit is cleared to 0, the CAN interface waits until it
detects 11 recessive bits, and then joins in the CAN bus
activity.
0: Normal operating mode
1: Transition to halt mode is requested
Rev. 2.00, 09/04, page 417 of 720