SH7047 Datasheet, PDF (188/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

9.10 On-chip Peripheral I/O Register Access
On-chip peripheral I/O registers are accessed from the bus state controller, as shown in Table 9.3.
Table 9.3 On-chip Peripheral I/O Register Access
On-chip
Peripheral
MTU,
PFC,
Module SCI POE INTC PORT CMT A/D UBC WDT DTC MMT HCAN2 H-UDI
Connected 8bit 16bit 16bit 16bit 16bit 16bit 16bit 16bit 16bit 16bit 16bit
bus width
16bit
Access
cycle
2cyc 2cyc 2cyc 2cyc 2cyc 2cyc 3cyc 3cyc 3cyc 2cyc 8cyc
*¹
*¹
*²
*²
*¹
*¹
*²
*²
*²
*¹
*²
2cyc
*¹
Notes: 1. Converted to the peripheral clock.
2. Converted to the system clock.
9.11 Cycles in which Bus is not Released
1. One bus cycle:
The bus is never released during a single bus cycle. For example, in the case of a longword
read (or write) in 8-bit normal space, the four memory accesses to the 8-bit normal space
constitute a single bus cycle, and the bus is never released during this period. Assuming that
one memory access requires two states, the bus is not released during an 8-state period.
8 bit
8 bit
8 bit
8 bit
Cycles in which
Bus is not Released
Figure 9.10 One Bus Cycle
9.12 CPU Operation when Program is In External Memory
In this LSI, two words (equivalent to two instructions) are normally fetched in a single instruction
fetch. This is also true when the program is located in external memory, irrespective of whether
the external memory bus width is 8 or 16 bits.
If the program counter value immediately after the program branched is an odd-word (2n+1)
address, or if the program counter value immediately before the program branches is an even-word
(2n) address, the CPU will always fetch 32 bits (equivalent to two instructions) that include the
respective word instruction.
Rev. 2.00, 09/04, page 148 of 720