SH7047 Datasheet, PDF (114/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

IRQOUT
NMI
IRQ0
IRQ1
IRQ2
IRQ3
UBC
H-UDI
DTC
MTU
CMT
MMT
A/D
SCI
WDT
HCAN2
I/O
Input
control
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
(Interrupt request)
ICR1
ICR2
ISR
Com-
parator
IPR
IPRA to IPRK
Interrupt
request
SR
I3 I2 I1 I0
CPU
DTER
DTC
Module bus
Bus
interface
INTC
UBC: User break controller
H-UDI: High-performance user debug interface
DTC: Data transfer controller
MTU: Multifunction timer unit
CMT: Compare match timer
MMT: Motor management timer
A/D: A/D converter
SCI:
Serial communications interface
WDT:
Watchdog timer
HCAN2:
Controller area network 2
I/O:
I/O port (Port output controller)
ICR1, ICR2: Interrupt control register
ISR:
IRQ status register
IPRA to IPRK: Interrupt priority level setting registers A to K
SR:
Status register
Figure 6.1 INTC Block Diagram
Rev. 2.00, 09/04, page 74 of 720