SH7047 Datasheet, PDF (348/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

10.9.2 Pin Configuration
Table 10.44 Pin Configuration
Name
Abbreviation
Port output enable input pins POE0–POE3
I/O
Input
Description
Input request signals to make high-
current pins high-impedance state
Table 10.45 shows output-level comparisons with pin combinations.
Table 10.45 Pin Combinations
Pin Combination
I/O
PE9/TIOC3B and PE11/TIOC3D Output
PE12/TIOC4A and PE14/TIOC4C Output
PE13/TIOC4B/MRES and
PE15/TIOC4D/IRQOUT
Output
Description
All high-current pins are made high-impedance
state when the pins simultaneously output low-level
for longer than 1 cycle.
All high-current pins are made high-impedance
state when the pins simultaneously output low-level
for longer than 1 cycle.
All high-current pins are made high-impedance
state when the pins simultaneously output low-level
for longer than 1 cycle.
10.9.3 Register Configuration
The POE has the two registers. The input level control/status register 1 (ICSR1) controls both
POE0–POE3 pin input signal detection and interrupts. The output level control/status register
(OCSR) controls both the enable/disable of output comparison and interrupts.
Input Level Control/Status Register 1 (ICSR1): The input level control/status register (ICSR1)
is a 16-bit readable/writable register that selects the POE0 to POE3 pin input modes, controls the
enable/disable of interrupts, and indicates status.
Rev. 2.00, 09/04, page 308 of 720