SH7047 Datasheet, PDF (552/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

16.8.4 Operation
Input Level Detection: When the input condition set in ICSR2 occurs on any one of the POE
pins, the MMT output pins go to the high-impedance state.
• Pins placed in the high-impedance state (the MMT's output pins)
The six pins PWOB, PWOA, PVOB, PVOA, PUOB, PUOA in the motor management timer
(MMT) are placed in the high-impedance state.
Note: These pins are in the high-impedance state only when each pin is used as the general
input/output function or MMT output pin.
1. Falling edge detection
When a transition from high- to low-level input occurs on a POE pin
2. Low level detection
Figure 16.19 shows the low level detection operation. Low level sampling is performed 16
times in succession using the sampling clock set in ICSR2. The input is not accepted if a high
level is detected even once among these samples.
The timing of entry of the MMT's output pins into the high-impedance state from the sampling
clock is the same for falling edge detection and low level detection.
Pφ
Sampling clock
POE input
PUOA
8, 16, or
128 clocks
High-impedance state
All low-level samples
[1]
At least one high-level
sample
[1]
[2]
[3]
[16] Flag set (POE accepted)
[2]
[13] Flag not set
Note: The other MMT output pins also go to the high-impedance state at the same timing.
Figure 16.19 Low Level Detection Operation
Exiting High-Impedance State: The MMT output pins that have entered the high-impedance
state by the input level detection are released from this state by restoring them to their initial states
by means of a power-on reset, or by clearing all the POE flags in ICSR2 (POE4F to POE6F: bits
12 to 14).
Rev. 2.00, 09/04, page 512 of 720