SH7047 Datasheet, PDF (301/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

10.7.6 Contention between TGR Write and Compare Match
When a compare match occurs in the T2 state of a TGR write cycle, the TGR write is executed
and the compare match signal is generated.
Figure 10.73 shows the timing in this case.
Pφ
Address
TGR write cycle
T1 T2
TGR address
Write signal
Compare
match signal
TCNT
N
N+1
TGR
N
M
TGR write data
Figure 10.73 Contention between TGR Write and Compare Match
Rev. 2.00, 09/04, page 261 of 720