SH7047 Datasheet, PDF (540/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

Requests to start A/D conversion is enabled by setting the bit TTGE in the timer control register
(TCNR) to 1.
Table 16.3 shows the relationship between A/D conversion start timing and operating mode.
Table 16.3 Relationship between A/D Conversion Start Timing and Operating Mode
Operating mode
A/D conversion start timing
Operating mode 1 (transfer at peak)
A/D conversion start at bottom
Operating mode 2 (transfer at bottom)
A/D conversion start at peak
Operating mode 3 (transfer at peak and bottom) A/D conversion start at peak and bottom
16.4.2 Output Protection Functions
Operating mode output has the following protection functions:
• Halting MMT output by external signal
The 6-phase PWM output pins can be placed in the high-impedance state automatically by
inputting a specified external signal. There are three external signal input pins. For details, see
section 16.8, Port Output Enable (POE).
• Halting MMT output when oscillation stops
The 6-phase PWM output pins are placed in the high-impedance state automatically when
stoppage of the clock input is detected. However, pin states are not guaranteed when the clock
is restarted.
16.5 Interrupts
When the TGFM (TGFN) flag is set to 1 in the timer status register (TSR) by a compare match
between TCNT and the TPDR register (2Td), and if the TGIEM (TGIEN) bit setting in the timer
control register (TCNR) is 1, an interrupt is requested. The interrupt request is cleared by clearing
the TGF flag to 0.
Table 16.4 MMT Interrupt Sources
Name
TGIMN
TGINN
Interrupt Source
Compare match between TCNT and TPDR
Compare match between TCNT and 2Td
Interrupt Flag
TGFM
TGFN
DTC Activation
Yes
Yes
The on-chip DTC can be activated by a compare match between TCNT and TPDR or between
TCNT and 2Td.
Rev. 2.00, 09/04, page 500 of 720