SH7047 Datasheet, PDF (150/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

On-chip ROM
On-chip RAM
On-chip
peripheral
module
CPU interrupt request
source clear control
Interrupt request
External
memory
External device
(memory-
mapped)
Register
control
Activation
control
Request
priority
control
Bus interface
DTMR
DTCR
DTSAR
DTDAR
DTIAR
DTER
DTCSR
DTBR
DTC module bus
DTC
Bus controller
Notes
DTMR: DTC mode register
DTCR: DTC transfer count register
DTSAR: DTC source address register
DTDAR: DTC destination address register
DTIAR: DTC initial address register
DTER: DTC enable register
DTCSR: DTC control/status register
DTBR: DTC information base register
Figure 8.1 Block Diagram of DTC
Rev. 2.00, 09/04, page 110 of 720