SH7047 Datasheet, PDF (138/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

7.2.2 User Break Address Mask Register (UBAMR)
The user break address mask register (UBAMR) consists of two registers: user break address mask
register H (UBAMRH) and user break address mask register L (UBAMRL). Both are 16-bit
readable/writable registers. UBAMRH specifies whether to mask any of the break address bits set
in UBARH, and UBAMRL specifies whether to mask any of the break address bits set in UBARL.
• UBAMRH Bits 15 to 0: specifies user break address mask 31 to 16 (UBM31 to UBM16)
• UBAMRL Bits 15 to 0: specifies user break address mask 15 to 0 (UBM15 to UBM0)
Initial
Bit
Bit Name Value
R/W
UBAMRH15 to UBM31 to All 0
R/W
UBAMRH 0 UBM16
UBAMRL15 to UBM15 to All 0
R/W
UBAMRL0
UBM0
Description
User Break Address Mask 31 to 16
0: Corresponding UBA bit is included in the
break conditions
1: Corresponding UBA bit is not included in
the break conditions
User Break Address Mask 15 to 0
0: Corresponding UBA bit is included in the
break conditions
1: Corresponding UBA bit is not included in
the break conditions
7.2.3 User Break Bus Cycle Register (UBBR)
The user break bus cycle register (UBBR) is a 16-bit readable/writable register that sets the four
break conditions.
Initial
Bit Bit Name Value R/W
15 to 8 
All 0
R
7
CP1
0
R/W
6
CP0
0
R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
CPU Cycle/DTC Cycle Select 1 and 0
These bits specify break conditions for CPU cycles or
DTC cycles.
00: No user break interrupt occurs
01: Break on CPU cycles
10: Break on DTC cycles
11: Break on both CPU and DTC cycles
Rev. 2.00, 09/04, page 98 of 720