SH7047 Datasheet, PDF (519/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

15.7 CAN Bus Interface
A bus transceiver IC is necessary to connect this LSI to a CAN bus. A Renesas HA13721
transceiver IC and its compatible products are recommended. Figure 15.16 shows a sample
connection diagram.
This LSI
120 Ω
Vcc
HRxD1
HTxD1
HA13721
MODE Vcc
Rxd CANH
Txd CANL
NC GND
NC
CAN bus
120 Ω
Note: NC: No Connection
Figure 15.16 High-Speed Interface Using HA13721
15.8 Usage Notes
15.8.1 Time Trigger Transmit Setting/Timer Operation Disabled
• The timer should not be operated during event trigger transmission (TCR15 = 0), or event
trigger may not be executed normally.
15.8.2 Reset
The HCAN2 is reset by a power-on reset, in hardware standby mode, and in software standby
mode. All the registers are initialized in a reset, but mailboxes MBx are not. After power-on,
however, mailboxes MBx are initialized, and their values are undefined. Therefore, mailbox
initialization must always be carried out after a power-on reset, a transition to hardware standby
mode, or software standby mode. The reset interrupt flag (IRR0) is always set after a power-on
reset or recovery from software standby mode. As this bit cannot be masked in the interrupt mask
register (IMR), if HCAN2 interrupt enabling is set in the interrupt controller without clearing the
flag, an HCAN2 interrupt will be initiated immediately. IRR0 should therefore be cleared during
initialization.
Rev. 2.00, 09/04, page 479 of 720