SH7047 Datasheet, PDF (405/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

12.5.2 Multiprocessor Serial Data Reception
Figure 12.13 shows a sample flowchart for multiprocessor serial data reception. If the MPIE bit in
SCR is set to 1, data is skipped until data with a 1 multiprocessor bit is sent. On receiving data
with a 1 multiprocessor bit, the receive data is transferred to RDR. An RXI interrupt request is
generated at this time. All other SCI operations are the same as in asynchronous mode. Figure
12.12 shows an example of SCI operation for multiprocessor format reception.
Start
1 bit
Data (ID1)
Stop Start
MPB bit bit
Data (Data1)
Stop
MPB bit
1
0 D0 D1
D7 1 1 0 D0 D1
D7 0
1 Idle state
(mark state)
MPIE
RDRF
RDR
value
ID1
MPIE = 0
RXI interrupt
request
(multiprocessor
interrupt)
generated
RDR data read If not this station’s ID,
and RDRF flag MPIE bit is set to 1
cleared to 0 in
again
RXI interrupt
processing routine
RXI interrupt request is
not generated, and RDR
retains its state
(a) Data does not match station’s ID
Start
1 bit
Data (ID2)
Stop Start
MPB bit bit
Data (Data2)
Stop
MPB bit
1
0 D0 D1
D7 1 1 0 D0 D1
D7 0
1 Idle state
(mark state)
MPIE
RDRF
RDR
value
ID1
ID2
Data2
MPIE = 0
RXI interrupt
request
(multiprocessor
interrupt)
generated
RDR data read and
RDRF flag cleared
to 0 in RXI interrupt
processing routine
Matches this station’s ID,
so reception continues,
and data is received in RXI
interrupt processing routine
MPIE bit is set to 1
again
(b) Data matches station’s ID
Figure 12.12 Example of SCI Operation in Reception (Example with 8-Bit Data,
Multiprocessor Bit, One Stop Bit)
Rev. 2.00, 09/04, page 365 of 720