SH7047 Datasheet, PDF (231/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

10.3.12 Timer Gate Control Register (TGCR)
TGCR is an 8-bit readable/writable register that controls the waveform output necessary for
brushless DC motor control in reset-synchronized PWM mode/complementary PWM mode.
These register settings are ineffective for anything other than complementary PWM mode/reset-
synchronized PWM mode.
Initial
Bit Bit Name value R/W Description
7

0
R
Reserved
This bit is always read as 1. Only 1 should be written to this
bit.
6
BDC
0
R/W Brushless DC Motor
This bit selects whether to make the functions of this
register (TGCR) effective or ineffective.
0: Ordinary output
1: Functions of this register are made effective
5
N
0
R/W Reverse Phase Output (N) Control
This bit selects whether the level output or the reset-
synchronized PWM/complementary PWM output while the
reverse pins (TIOC3D, TIOC4C, and TIOC4D) are on-
output.
0: Level output
1: Reset synchronized PWM/complementary PWM output
4
P
0
R/W Positive Phase Output (P) Control
This bit selects whether the level output or the reset-
synchronized PWM/complementary PWM output while the
positive pin (TIOC3B, TIOC4A, and TIOC4B) are on-output.
0: Level output
1: Reset synchronized PWM/complementary PWM output
3
FB
0
R/W External Feedback Signal Enable
This bit selects whether the switching of the output of the
positive/reverse phase is carried out automatically with the
MTU/channel 0 TGRA, TGRB, TGRC input capture signals
or by writing 0 or 1 to bits 2 to 0 in TGCR.
0: Output switching is carried out by external input (Input
sources are channel 0 TGRA, TGRB, TGRC input
capture signal)
1: Output switching is carried out by software (TGCR's UF,
VF, WF settings).
Rev. 2.00, 09/04, page 191 of 720