SH7047 Datasheet, PDF (168/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

8.3.6 DTC Execution State Counts
Table 8.5 shows the execution state for one DTC data transfer. Furthermore, Table 8.6 shows the
state counts needed for execution state.
Table 8.5 Execution State of DTC
Mode
Vector Read
I
Register
Information
Read/Write
J
Normal
1
7
Repeat
1
7
Block transfer 1
7
N: block size (default set values of DTCRB)
Data Read
K
1
1
N
Data Write
L
1
1
N
Internal
Operation
M
1
1
1
Table 8.6 State Counts Needed for Execution State
Access Objective
On-chip On-chip Internal I/O
RAM ROM Register
Bus width
Access state
32
32
32
32
1
1
2*¹
3*²
Execution Vector read
S

1
I
state
Register information S
1
1
J
read/write




Byte data read
S_K
1
1
2
3
Word data read
S_K
1
1
2
3
Long word data read S_K
1
1
4
6
Byte data write
S_L
1
1
2
3
Word data write
S
1
1
2
3
L
Longword data write S
1
1
4
6
L
Internal operation
S
1
1
1
1
M
Notes: 1. Two state access module: port, INT, CMT, SCI, etc.
2. Three state access module: WDT, UBC, etc.
External
Device
8
2
4
8
2
4
8
2
4
8
1
The execution state count is calculated using the following formula. Σ indicates the number of
transfers by one activating source (count + 1 when CHNE bit is set to 1).
Execution state count = I · S_I + Σ (J · S_J + K · S_K + L · S_L) + M · S_M
Rev. 2.00, 09/04, page 128 of 720