SH7047 Datasheet, PDF (498/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

Initial
Bit Bit Name Value R/W Description
1
TSR1
0
R
Compare Match Flag 0
Indicates that a compare-match condition occurred in
compare match register 0 (TCMR0). When the value set
in TCMR0 matches the timer value (TCMR0 = TCNTR),
this bit is set.
Note: This bit is not set if the TCMR0 value is H'0000.
Also, this bit is read-only and is cleared when
IRR14 (timer compare match interrupt flag 0) is
cleared.
0: Timer compare match has not occurred
1: Timer compare match has occurred (TCMR0)
[Clearing condition]
• Writing 1 to IRR14
[Setting condition]
• TCMR0 = TCNTR
0
TSR0
0
R
Timer Overflow Flag
Indicates that the timer has overflowed and is reset to
H'0000.
0: Timer has not overflowed
1: Timer has overflowed
[Clearing condition]
• Writing 1 to IRR13
[Setting condition]
• When the timer value changes from H'FFFF to H'0000
15.3.20 Local Offset Register (LOSR)
LOSR is a 16-bit readable/writable register. The purpose of this register is to set a local offset to
the timer counter (TCNTR). Whenever TCNTR is cleared by overflow, timer compare match, or
CAN-ID compare match, TCNTR starts counting from the value set in this register.
Initial
Bit Bit Name Value R/W
15 to 0 LOSR15 to All 0 R/W
LOSR0
Description
Local Offset Register
When the timer counter (TCNTR) is cleared by overflow,
timer compare match, or CAN-ID compare match, TCNTR
starts counting from the value set in LOSR.
Rev. 2.00, 09/04, page 458 of 720