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| SH7047 Datasheet, PDF (672/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series | |||
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CK
A17 to A0
T1
TW
TW
TWO
T2
CSn
RD
(read)
D7 to D0
(read)
WRx
(write)
D7 to D0
(write)
WAIT
tWTS tWTH
tWTS tWTH
Note: tRDH: Specified from the negate timing of A17 to A0, CSn, or RD, whichever is first.
Figure 25.12 Basic Cycle (Two Software Waits + Waits by WAIT Signal)
Rev. 2.00, 09/04, page 632 of 720
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