SH7047 Datasheet, PDF (454/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

Initial
Bit Bit Name Value R/W Description
12 TST4
0
R/W Auto Acknowledge Mode
Allows HCAN2 to generate its own acknowledge bit in
order to enable Self Test. In order to achieve the Self Test
mode, there are two type settings for this. One is to set
(TST0 = 1 & TST1 = 1 & TST2 = 1), so that the Tx value
can be internally provided to the Rx. The other way is to
set (TST0 = 0 & TST1 = 0 & TST2 = 0) and connect the
Tx and Rx onto the CAN bus so that the data can be
transmitted via the CAN bus.
0: HCAN2 does not generate its own acknowledge bit
1: HCAN2 generates its own acknowledge bit
11 TST3
0
R/W Disable Error Counters
Enables/disables the error counters (TEC/REC) to be
functional. When this bit is enabled, the error counters
(TEC/REC) remain unchanged and holds the current
value. When this bit is disabled, the error counters
(TEC/REC) function according to the CAN specification.
0: Error counters (TEC/REC) function according to the
CAN specification
1: Error counters (TEC/REC) remain unchanged and
holds the current value
10 TST2
0
R/W Disable Rx Input
Controls the Rx to be supplied into the CAN Interface
block. When this bit is enabled, the Rx pin value is
supplied into the CAN Interface block. When this bit is
disabled, the Rx value for the CAN block always remains
recessive or the Tx value internally connected if TST0 =
1.
0: External Rx pin is supplied for the CAN Interface block
1: [TST0 = 0] Rx always remain recessive for the CAN
Interface block
[TST0 = 1] Tx is internally supplied for the CAN
Interface block
Rev. 2.00, 09/04, page 414 of 720