SH7047 Datasheet, PDF (464/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

Initial
Bit Bit Name Value R/W Description
9
IRR9
0
R
Unread Message Interrupt Flag
Status flag indicating that a message has been received
but the existing message in that mailbox has not yet been
read due to the corresponding RXPR or RFPR set to 1.
The received message is either ignored (overrun) or
overwritten depending on the NMC (new message
control) bit.
Note: To clear this bit, clear the UMSR bit by writing 1 to
corresponding UMSR bit. Writing 0 has no effect.
0: No message overrun or overwritten
1: Receive message overrun or overwritten
[Clearing condition]
• All the UMSR bits are cleared
[Setting conditions]
• Message is received while the corresponding RXPR
or RFPR = 1 and MBIMR = 0
• Any UMSR bit is set
8
IRR8
0
R/W Mailbox Empty Interrupt Flag
This bit is set when at least one TXPR bit is cleared. It is
a status flag indicating that the mailbox is now ready to
accept a new transmit message. In effect, this bit is set
when any bit in TXACK or ABACK is set, therefore, this
bit is automatically cleared when all the TXACK and
ABACK bits are cleared.
0: Transmission or transmission abort of a message is not
yet carried out.
1: Message has been transmitted or aborted, and new
message can be stored
[Clearing condition]
• When all the TXACK and ABACK bits are cleared
[Setting condition]
• When one of the TXPR (transmit wait) bits is cleared
by completion of transmission or completion of
transmission abort, i.e., when a TXACK or ABACK bit
is set (if MBIMR = 0).
Note: This bit does not indicate that all TXPR bits are
reset.
Rev. 2.00, 09/04, page 424 of 720