SH7047 Datasheet, PDF (66/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

Addressing
Mode
PC relative
addressing
Immediate
addressing
Instruction
Format
Effective Address Calculation
Rn
The effective address is the sum of the register PC
and Rn.
Equation
PC + Rn
PC
+
PC + Rn
#imm:8
#imm:8
#imm:8
Rn
The 8-bit immediate data (imm) for the TST, AND, 
OR, and XOR instructions is zero-extended.
The 8-bit immediate data (imm) for the MOV, ADD, 
and CMP/EQ instructions is sign-extended.
The 8-bit immediate data (imm) for the TRAPA

instruction is zero-extended and then quadrupled.
2.4.3 Instruction Format
The instruction formats and the meaning of source and destination operand are described below.
The meaning of the operand depends on the instruction code. The symbols used are as follows:
• xxxx: Instruction code
• mmmm: Source register
• nnnn: Destination register
• iiii: Immediate data
• dddd: Displacement
Rev. 2.00, 09/04, page 26 of 720