SH7047 Datasheet, PDF (448/764 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTMRISC engine Family/SH7000 Series

• Other feature
The DTC can be activated by message receive mailbox (HCAN2 mailbox 0 only)
• Module standby mode can be set
• Read section 15.8, Usage Notes.
CAN interface
REC
HRxD1
HTxD1
TEC
BCR
Transmit buffer
Receive buffer
Microprocessor
interface (MPI)
MCR
IRR
GSR
IMR
TXPR TXACK
TXCR ABACK
RXPR
RFPR
MBIMR UMSR
Mailbox control
TCNTR LOSR
TCR
ICR
TSR
TCMR
16-bit timer
Mailbox0 Mailbox8 Mailbox16 Mailbox24
Mailbox1 Mailbox9 Mailbox17 Mailbox25
Mailbox2 Mailbox10 Mailbox18 Mailbox26
Mailbox3 Mailbox11 Mailbox19 Mailbox27
Mailbox4 Mailbox12 Mailbox20 Mailbox28
Mailbox5 Mailbox13 Mailbox21 Mailbox29
Mailbox6 Mailbox14 Mailbox22 Mailbox30
Mailbox7 Mailbox15 Mailbox23 Mailbox31
Mailboxes 0 to 31 (RAM)
• Message control
• Message data
• LAFM/Tx-trigger time
Figure 15.1 HCAN2 Block Diagram
Microprocessor Interface (MPI): The MPI allows communication between the CPU and
HCAN2’s registers/mailboxes to control the timer unit and memory interface. It also contains the
wakeup control logic that detects the CAN bus activities and notifies to the MPI and other parts of
the HCAN2 so that the HCAN2 can automatically exit HCAN2 sleep mode.
Mailbox (MB): The mailbox is essentially arrayed on the RAM as message buffers. There are 32
mailboxes, and each mailbox has the following information.
• CAN message control
Rev. 2.00, 09/04, page 408 of 720